Nickel-silicide (NiSi) is an important and frequently used contact material for semiconductor devices such as field-effect-transistors (FETs), which are usually applied in the source (S), drain (D), and/or gate (G) regions of a FET. On the other hand, while being suitable as a contact material, NiSi is also known as a frequent cause of device defects which may be manifested by NiSi formed underneath masking spacer edges and particularly by NiSi formed in the direction of junction of a FET. These defects, which are classified collectively as encroachment defects hereinafter, have been observed in almost every technology node since 65 nm node, may potentially cause device failure due to S/D-well and/or S/D-gate current leakage. Therefore, NiSi encroachments (such as “pipe” defect and “tunnel”defect as known in the art) have been known as “killer defects” in the process of FET formation.
Based upon past experience, tendency of causing encroachment defects during NiSi formation seems to differ between n-type doped FET (NFET) devices and p-type doped FET (PFET) devices, and between PFET SOI (silicon-on-insulator) devices and PFET eSiGe (embedded SiGe) devices. It has been tried to use a nickel-platinum alloy target material, for example, of Ni5%Pt having about 5% platinum (Pt) (in percentage of atom, same throughout this document) in forming nickel-silicide (more precisely platinum-containing nickel-silicide) for 65 nm node, and the NiSi formed thereby has demonstrated to eradicate the “pipe” defects which were previously characterized as predominant on NFET and PFET SOI devices. At the 45 nm node, significant yield improvement has been achieved by using a Ni10%Pt alloy target material, having a higher 10% platinum (Pt) content, to fix the “tunnel”defects on PFET eSiGe devices which would otherwise be found in conventional NiSi. The “tunnel”defects in 45 nm node have been known of having significantly larger size/length than the “pipe”defects found in 65 nm node.
Unfortunately, the switch to using higher Pt content nickel-platinum alloy is also accompanied by a resistance penalty that is particularly less forgiving for technologies that integrate eDRAM, where strap resistance and perhaps retention yield is highly sensitive to resistance (Rs) of the silicide. The penalty associated with Rs cannot be easily remedied by, for example, simply increasing the silicide thickness due to the narrow process window that is available for the thickness of NiSi. In addition, the switch to using higher Pt content nickel-platinum alloy is further accompanied by a process tendency of forming partial FUSI (fully silicided) gates which may degrade device drive current. Although a low temperature nickel-silicide formation process was later found to be able to fix the partial FUSI defect, the process caused further increases of silicide resistance. Independent from the above technical concerns, the semiconductor industry has also shown a reluctance to migrate towards a silicide process with higher Pt content due to potential higher cost of the target material.